Multiple Recurring Instruction Set Computing and Implied Instruction Set Computing
From UCSC Wiki
Presenter: Mr. Sirinath Dharmasena
abstract
"The Instruction Set Architecture (ISA) used in this computer architecture runs instructions in a highly parallel way. These processors will have loosely coupled functional units (FUs). These FUs will have registers hardwired to them. Useful computation is achieved by moving the registers from one to another. This way data can be pushed through a series of FUs which transforms it. When many such moves are made in parallel, it facilitates the execution of many instructions. Further details of this can be found in the attached paper. In a nutshell, this design would speed up the computation by making instructions as parallel as possible. Furthermore this does not have a decode phase. This is achieved by making the instruction to be arranged in a multiple recurring manner, so that the instruction is implied by its position, eliminating the need of using an op code to identify the instructions
This processor would increase the execution speed of certain classes of algorithms like Neural Networks by many folds. More speed can be gained when the dependencies between instructions are lesser. Generally, some degree of performance improvement is expected. Therefore, this can be used in super computing and application specific computing. Also since this architecture is a simplification of current architecture, the development as well as testing would be easier, cheaper and less problematic."
Further details can be foud at: http://sirinath1978m.googlepages.com/
